The present invention relates to computer systems, and more particularly, to computer systems for processing system management interrupts.
Most modem computer systems, such as those based on the Intel(copyright) Pentium(copyright) processor, are equipped with a special processing mode known as system management mode. In system management mode, the computer processor executes software instructions accessed from a completely separate address space than the normal address space in which the system memory is mapped. That is, the physical system memory is mapped according to a normal address mapping when the processor is not in system management mode and is mapped according to a system management mode address mapping when the processor is in system management mode.
xe2x80x9cSystem management mode is commonly used when implementing control features such as power management. A common implementation of power management is to turn off power to a device when it has been idle for a programmed amount of time. When the device is accessed again, power is reapplied and the input/output (I/O) instruction that caused the access is executed.xe2x80x9d
A typical prior art computer system that implements system management mode includes a processor coupled by a processor bus to a North bridge that includes a memory controller coupled to a system memory. The North bridge typically is coupled by a primary computer bus to a South bridge which is coupled by a secondary computer bus to various computer devices, such as a keyboard. The South bridge typically is coupled directly to a System Management Interrupt (SMI) pin of the processor to enable the South bridge to submit an SMI request by driving the SMI pin.
Suppose the keyboard is inactive for an extended amount of time. Many current South bridges will detect that the keyboard is not being used and will submit an SMI request to the processor. In response, the processor saves state information stored in internal registers to a predetermined portion of system management memory and jumps to an entry point in system management memory where an SMI handler routine is located. The processor executes the SMI handler routine to service the power management request by saving the state of the inactive device to system management memory and powering-down the device. Upon completing its task as specified by the SMI handler routine, the processor retrieves and restores the saved processor state from system management memory, exits system management mode, and continues normal program execution. The processor exits system management mode and returns to normal mode in response to a return to system management mode (RSM) instruction at the end of the SMI handler routine.
A problem with prior art implementations of system management mode is that SMI requests can only be processed serially. After an SMI request is recognized, the SMI pin is masked by the processor until the SMI handler finishes processing the SMI request. If another SMI request is asserted while a current SMI request is being serviced, the second SMI request is latched and can only be serviced after the SMI handler completes servicing the first SMI request. If a third SMI request was attempted while the first SMI request was being serviced, the third SMI request would be lost. Such serial processing of SMI requests prevents prior art computer systems from implementing time-sensitive applications using system management mode.
An additional problem of prior art systems is that the SMM memory space is limited to 64 KB of memory. Given that some of the SMM memory space is needed to store the state of the CPU and devices of the computer, there is somewhat less than 64 KB for the SMI handler routine. As a result, the services that can be provided by prior art SMI handler routines are limited to those that are necessary and that can be provided by programming that fits within the limited SMM memory space.
The invention is directed to a computer system for processing system management interrupt (SMI) requests. The computer system includes first and second system management (SM) requesters each structured to assert SMI requests. A processor coupled to the first and second SM requesters is structured to activate a system management mode in response to receiving an SMI request from one of the SM requesters. A memory controller coupled to the processor and a system memory is structured to access a first SMI handler routine in the system memory if the processor activates system management mode in response to receiving an SMI request from the first SM requester. The memory controller is structured to access a second SMI handler routine in the system memory if the processor activates system management mode in response to receiving an SMI request from the second SM requester. Employing separate SMI handlers enables different SM requesters to instigate system management mode for different purposes. In one embodiment, the method enables three SMI handler routines to be employed.
In another aspect of the invention, different SM requesters can be provided with different priority levels such that high priority SMI requests can be serviced without waiting for lower priority system management interrupts to be serviced completely. In particular, the processor executes a first SMI handler routine in response to receiving a first SMI request from a first SM requester. In response to the processor receiving a second SMI request asserted by a second SM requester, the memory controller determines whether the second SMI request has been assigned a higher priority than the first SMI request. If so, then the memory controller causes the processor to interrupt executing the first SMI handler routine and execute a second SMI handler routine. Otherwise, the memory controller allows the processor to complete executing the first SMI handler routine and then execute the second SMI handler routine.